FPGA验证有用的脚本

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在芯片RTL设计完成后， UVM仿真验证和FPGA原型验证可以同时展开。

本篇记录一下FPGA prototype 常用的脚本。

synplify 综合

  1. 使用synplify综合的时候， 工具不能读入filelist， 所以需要将filelist转成一个*.v 文件。
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import os

file_rtl = "../filist/file_rtl.f"
obj = open(file_rtl, 'r')


f2 = open("../filist/file_syn.v", 'w')
data = ""

for line in obj.readlines():
  line.strip();  #remove white space in a line
  # if this line is empty or the comment lines
  if line == '\n' or line.startswith('//'):
    f2.write(line)
  else:
    line = line[:-1]; # remove the last  '\n'
    f2.write("`include " + '\"' + line + '\"'+ '\n')

f2.write("`include " + '\"' + '../src/mipsfpga_nexysvideo.v' + '\"' + '\n')
f2.write("`include " + '\"' + '../src/ip/clk_wiz_0/clk_wiz_0.v' + '\"' + '\n')
f2.write("`include " + '\"' + '../src/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v' + '\"' + '\n')


obj.close()
f2.close()

Vivado脚本

synplify综合完成后会产生 sdc文件和网表文件(*.edf)

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#################################################
###     SET DESIGN VARIABLES      ###
#################################################
set DesignName  	"mipsfpga"
set FamilyName  	"ARTIX7"
set DeviceName  	"XC7A200T"
set PackageName 	"SBG484"
set SpeedGrade  	"-1"
set TopModule   	"mipsfpga_nexysvideo"
set PartName    	"XC7A200TSBG484-1"
set DcpFile    	""
set InputMode   	"EDIF"
set Flow   		"Standard" ;#Flow can be set to "Incremental" or "Standard"
set StrategyMode	"default";
#StrategyMode can be set to "timing_qor","fast_turn_around" or "default" 
#Only one StrategyMode can be specified at a time
	
#################################################
###     ENABLE BETA LICENSE      ###
## 		Beta feature 		 ## 
#################################################
if {${DeviceName} == "XCVU440"} {enable_beta_device}

#################################################
###     SETUP STRATEGY AND FLAGS    ###
#################################################
puts "StrategyMode is ${StrategyMode}"
switch -- $StrategyMode {
    "timing_qor" {
        set opt_design_flags    "-directive Explore"
        set place_design_flags  "-directive Explore"
        set route_design_flags  "-directive Explore"
    }
    "fast_turn_around" {
        set opt_design_flags    "-directive RuntimeOptimized"
        set place_design_flags  "-directive RuntimeOptimized"
        set route_design_flags  "-directive RuntimeOptimized"
    }
    default {
        set opt_design_flags    ""
        set place_design_flags  ""
        set route_design_flags  ""
    }
}
set write_bitstream_enable  "1"
#################################################
###     SETUP DESIGN     ###
#################################################
set_property target_part ${PartName} [current_fileset -constrset]
set_property design_mode GateLvl [current_fileset]
reset_property SEVERITY [get_drc_checks REQP-46]

### Turn off a restriction on the number of clock objects allowed in a list for create_*clock commands
catch {set_param sta.maxSourcesPerClock -1}

### Suppresses warning about multiple objects in a clock list
catch {set_msg_config -id {Constraints 18-633} -suppress}

### Demotes error to warning about GTGREFCLK_ACTIVE inserted for multiview instrumentation
catch {set_property SEVERITY {warning} [get_drc_checks REQP-46]}
catch {set_property SEVERITY {warning} [get_drc_checks REQP-56]}

### Promotes critical warning on unroutability to an error
catch {set_msg_config -id {Route 35-162} -new_severity ERROR}

if {${InputMode} == "EDIF"} {
     set_property edif_top_file ${DesignName}.edf [current_fileset]
     if {[file exists ${DesignName}.edf]} { read_edif ${DesignName}.edf }    
     if {[file exists ${DesignName}_edif.xdc]} { read_xdc ${DesignName}_edif.xdc } 
     if {[file exists ${DesignName}_floorplan.xdc]} { read_xdc ${DesignName}_floorplan.xdc }   
     set TopModule [find_top]
} 

if {${InputMode} == "VM"} {
     if {[file exists ${DesignName}.vm]} { read_verilog ${DesignName}.vm }    
     if {[file exists ${DesignName}.xdc]} { read_xdc ${DesignName}.xdc }  
     if {[file exists ${DesignName}_floorplan.xdc]} { read_xdc ${DesignName}_floorplan.xdc }  
     set TopModule [find_top]
     set_property top ${TopModule} [current_fileset] 
}


read_xdc pin_loc.xdc

#################################################
###    RUN DESIGN     ###
#################################################
#run link_design
link_design
if {[file exists "clock_groups.tcl"]} {source clock_groups.tcl}
#Evaluate options and run opt_design
eval opt_design $opt_design_flags

###     FOR INCREMENTAL FLOW     ###
puts "Flow is ${Flow}"
if {${Flow} == "Incremental"} {
	#Use DCP from previous P&R run for Incremental Flow
	if {[file exists "${DesignName}.dcp"]} {
	puts "Using ${DesignName}.dcp for Incremental Place and Route" 
	read_checkpoint -incremental ${DesignName}.dcp
	report_incremental_reuse
	} else {
	puts "${DesignName}.dcp does not exist. Running Place and Route" 
	}
}
#Evaluate options and run place_design
eval place_design $place_design_flags
write_checkpoint -force post_place.dcp
	
#Evaluate options and run route_design
eval route_design $route_design_flags
#set_property BITSTREAM.General.UnconstrainedPins {Allow} [current_design]
write_checkpoint -force ${DesignName}.dcp

#################################################
###     GENERATE REPORTS     ###
#################################################
report_utilization -file area.txt
report_utilization -slr -file slr.txt
config_timing_corners -corner Slow -delay_type max
config_timing_corners -corner Fast -delay_type none
report_timing_summary -nworst 3 -max_paths 3
config_timing_corners -corner Slow -delay_type none
config_timing_corners -corner Fast -delay_type min
report_timing_summary -nworst 3 -max_paths 3
report_clock_utilization -verbose -file clock_utilization.txt
report_io -file pinloc.txt
report_drc -file post_route_drc.txt
report_clock_interaction -file ${DesignName}_clock_interaction.rpt 
write_xdc -no_fixed_only -constraints valid -force ${DesignName}_post_par.xdc

#################################################
###     SAVE VIVADO PROJECT     ###
#################################################
save_project_as -force ${DesignName}
save_constraints -force

#################################################
###     GENERATE BITSTREAM     ###
#################################################
if {${write_bitstream_enable} == "1"} {
	set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN {Enable} [current_design]
	set_property BITSTREAM.GENERAL.COMPRESS {True} [current_design]
	#run write_bitstream
	write_bitstream -force ${DesignName}.bit
}